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目录
摘要
前言
一、Differential clock timing 差分系统时钟 CK 时序
1.1 Average time for clock signal - tCK(avg)
1.2 Average time for clock signal in high state - tCH(avg)
1.3 Average time for clock signal in low state - tCL(avg)
1.4 Absolute time for clock signal - tCK(abs)
1.5 Absolute time for clock signal in high state - tCH(abs)
1.6 Absolute time for clock signal in low state - tCL(abs)
1.7 Periodic jitter for clock signal - tJIT(per)
1.8 Cycle-to-cycle jitter for clock signal - tJIT(cc)
二、Differential write clock timing 差分写时钟 WCK 时序
2.1 Average write clock period - tWCK(avg)
2.2 Average time for write clock signal in high state - tWCKH(avg)
2.3 Average time for write clock signal in low state - tWCKL(avg)
2.4 Absolute time for write clock signal - tWCK(abs)
2.5 Absolute time for write clock signal in high state - tWCKH(abs)
2.6 Absolute time for write clock signal in low state - tWCKL(abs)
2.7 Periodic jitter for write clock signal - tJIT(per)_WCK
2.8 Cycle-to-cycle jitter for write clock signal - tJIT(cc)_WCK
2.9 Number of errors in write clock data - tERR(nper_WCK)
三、WCK to CK timing 相位偏移
四、Single-ended mode clock timing CK 单端模式时序
4.1 Clock single-ended CK pulse at Vddq/2±VCKIVW/2 - tCKHL
4.2 Clock single-ended CK positive pulse at Vddq/2 - tCKH
4.3 Clock single-ended CK negative pulse at Vddq/2 - tCKL
五、Single-ended mode write clock timing WCK 单端模式时序
5.1 Write clock single-ended WCK pulse at Vddq/2±VCKIVW/2 - tWCKHL
5.2 Write clock single-ended WCK positive pulse at Vddq/2 - tWCKH
5.3 Clock single-ended WCK negative pulse at Vddq/2 - tWCKL
小结
摘要
时钟质量直接决定 LPDDR5 系统能否稳定工作。本篇完整解读系统时钟 CK、写时钟 WCK 的全套时序指标:平均 / 绝对周期、高低电平脉冲宽度、周期性抖动 tJIT (per)、周期间抖动 tJIT (cc)、多周期累积误差 tERR、WCK‑CK 相位偏移`tWCK2CK`,以及单端模式 CK/WCK 脉冲时序;解释每个指标物理含义、统计窗口、计算公式,给出工程测试注意事项。
前言
LPDDR5 拥有两套差分时钟:系统时钟`CK_t/CK_c`,写时钟`WCK_t/WCK_c`。CK 用于命令地址采样;WCK 专门用于写 DQ 数据采样。两套时钟都需要测试周期、占空比、各类抖动,同时存在 WCK 相对于 CK 的相位对齐要求 WCK2CK leveling。很多测试失败来源于对抖动统计窗口、单端模式时