企业官网建设流程全解析

{reg: [ {bits: 8, name: "TLB Entry(le47)", type:4}, {bits: 16, name: "Rsvd", type:0}, {bits: 8, name: "RAMID=0x04", type:4}, {bits: 32, name: "", type:0}, {bits: 6, name: "TLB Entry(le47)", type:4}, {bits: 18, name: "Rsvd", type:0}, {bits: 8, name: "RAMID=0x0A", type:4}, {bits: 32, name: "", type:0}, {bits: 8, name: "Index", type:4}, {bits: 10, name: "Rsvd", type:0}, {bits: 3, name: "Way0~4", type:4}, {bits: 3, name: "Rsvd", type:0}, {bits: 8, name: "RAMID=0x18", type:4}, {bits: 32, name: "", type:0}, {bits: 1, name: "vld", type:7}, {bits: 4, name: "TLB Attr", type:4}, {bits: 2, name: "TLBRgm", type:4}, {bits: 16, name: "VMID[15:0]", type:3}, {bits: 16, name: "ASID", type:3}, {bits: 5, name: "TLBAttr", type:4}, {bits: 1, name: "I.S.", type:3}, {bits: 1, name: "O.S.", type:3}, {bits: 4, name: "TLBAttr", type:4}, {bits: 3, name: "PageSize", type:4}, {bits: 3, name: "Mem Attr", type:4}, {bits: 3, name: "TLB Attr", type:4}, {bits: 5, name: "Virt Addr[16:12]", type:3}, {bits: 32, name: "Virtual Addr[48:17]", type:3}, {bits: 28, name: "Physical Addr[39:12]", type:3}, {bits: 1, name: "N-s.", type:4}, {bits: 3, name: "?", type:0}, {bits: 1, name: "vld", type:7}, {bits: 16, name: "VMID[15:0]", type:3}, {bits: 16, name: "ASID", type:3}, {bits: 2, name: "TLBRgm", type:3}, {bits: 1, name: "N-s.", type:4}, {bits: 3, name: "PageSize", type:4}, {bits: 11, name: "?", type:0}, {bits: 3, name: "Mem Attr", type:4}, {bits: 4, name: "?", type:0}, {bits: 1, name: "I.S.", type:3}, {bits: 1, name: "O.S.", type:3}, {bits: 3, name: "?", type:0}, {bits: 2, name: "VirtAddr[13:12]", type:3}, {bits: 35, name: "VirtAddr[48:14]", type:3}, {bits: 28, name: "Physical Addr[39:12]", type:3}, {bits: 1, name: "?", type:0}, // {bits: 2, name: "Rsvd", type:0}, {bits: 4, name: "coalesced TLB", type:7}, {bits: 1, name: "③", type:7}, {bits: 10, name: "Rsvd", type:0}, {bits: 3, name: "PageSize", type:4}, {bits: 28, name: "Physical Addr[39:12]", type:3}, {bits: 4, name: "Rsvd", type:0}, {bits: 3, name: "Mem Attr", type:4}, {bits: 1, name: "Rsvd", type:0}, {bits: 1, name: "I.S.", type:3}, {bits: 1, name: "O.S.", type:3}, {bits: 1, name: "N-g.", type:3}, {bits: 5, name: "Rsvd", type:0}, {bits: 6, name: "Rsvd", type:0}, {bits: 1, name: "N-s.", type:4}, {bits: 29, name: "VirtAddr[48:20]", type:3}, {bits: 1, name: "①", type:4}, {bits: 1, name: "②", type:4}, {bits: 16, name: "ASID[15:0]", type:3}, {bits: 10, name: "VMID[9:0]", type:3}, {bits: 6, name: "VMID[15:10]", type:3}, {bits: 2, name: "Tranlation regime", type:4}, {bits: 56, name: "Rsvd", type:0}, {bits: 64, name: "I.S.:InnerShared, O.S.: OuterShared, N-s.:Non-secure, N-g.:NonGlobal, TLBRgm:TLB Regime ", }, {bits: 64, name: "①:PrefetchTranslation, ②:WalkCacheEntry, ③:Indicates that the entry is coalesced and holds translations for four contiguous pages.", }, ], config: {hspace: 1800, lanes: 12, bits: 64*12,vflip: false, hflip: true, compact:true,label: {right: ["L1 instr. TLB location enc.","L1 data TLB location enc.","L2 TLB encoding","L1 instr. TLB cache format","...","L1 data TLB cache format","..."," L2 TLB format","...","...","缩写","..."]}, }}

{reg: [ {bits: 1, name: "SB_VLD ", type:4}, {bits: 2, name: "MSID[1:0] ", type:0}, {bits: 16, name: "ASID ", type:4}, {bits: 16, name: "VMID ", type:0}, {bits: 10, name: "VA[48:39] ", type:4}, {bits: 2, name: "S2_LVL[1:0] ", type:0}, {bits: 1, name: "IS ", type:4}, {bits: 1, name: "OS ", type:0}, {bits: 4, name: "ATTR ", type:4}, {bits: 1, name: "S2_DBM ", type:0}, {bits: 1, name: "S2AP1 ", type:4}, {bits: 1, name: "NS ", type:0}, {bits: 1, name: "S2_XN ", type:0}, {bits: 1, name: "S2_PXN ", type:0}, {bits: 1, name: "S1_XN ", type:0}, {bits: 1, name: "S1_PXN ", type:0}, {bits: 28, name: "PA ", type:0}, {bits: 1, name: "sb_gsize ", type:0}, {bits: 7, name: "---------- ", type:0}, {bits: 32, name: "mm_tc_sb_alloc_non_crit_data_t3[88:0] ", type:0}, ], config: {hspace: 1800, lanes: 4, bits: 32*4,vflip: false, hflip: true, compact:true,label: {right: ["",]}, }}